MODULE DSP_DAC TITLE 'ADSP-21061 Sharc to DAC interface CPLD' "****************************************************************************** " Filename: LATTEQNS.ABL " Created on: Friday 13-August-1999, 18:00, TVJM " Revision History: " -Wednesday 1-September-1999, 14:38, TVJM: Added RESERVE_PINS for ACK & SW pins. " -Tuesday 31-August-1999, 21:41, TVJM: Removed .ACLR from MUX0 symbols " and .ASET from MUX1 symbols. " -Tuesday 31-August-1999, 21:20, TVJM: Restored temporary trials. " -Tuesday 31-August-1999, 01:31, TVJM: Added SCP/ECP to critical paths. " -Monday 30-August-1999, 23:35, TVJM: Added pin numbers from tonite's layout. " -Friday 27-August-1999, 17:30, TVJM: Added pin numbers from preliminary layout. " -Friday 27-August-1999, 16:35, TVJM: Removed !SRESET from all mux enable " output enables; all mux enable output-enables are now enabled during reset. " -Friday 27-August-1999, 14:25, TVJM: Added property statement comments. " -Thursday 26-August-1999, 23:10, TVJM: Removed unused WR input and ACK output. " -Thursday 26-August-1999, 22:40, TVJM: Added property statements. " -Thursday 26-August-1999, 21:50, TVJM: Removed asynchronous presets/resets " where not needed due to device fitting errors. " -Sunday 15-August-1999, 17:00, TVJM: Added programming commentary from prior " file MACHEQNS.DOC. " Created by: Tom V.J. Maglione, 29 Rice Rd, Wayland, MA 01778 (508) 655-9120 " Purpose: This file contains the source code for programming the LATTICE " ispLSI2064E-200LT CPLD for controlling the Sharc ADSP-21061 clocked " at 50MHz. interfaced to the AD768 D/A converter and several muxes. "****************************************************************************** "**************************************************************************** " NOTES: " 1. This file is designed to generate hardware to be used under the following " programming conditions on the Sharc ADSP-21061: " A. External memory bank 0 is setup for 48-bit program memory; " B. External memory bank 0 is programmed for wait state mode 1: " internal wait states only (EB0WM = binary 01 in WAIT register); " C. External memory bank 0 is programmed for 1 wait state " with bus idle cycle (EB0WS = binary 001 in WAIT register); " D. Bus idle cycle only occurs after every read cycle, but this " application does not generate reads to Memory Space 0; " E. External ACK remains unused and does not need to be pulled up or down; " F. One internal wait state extends the ADSP-21061 Sharc address bus, " data bus, /MS0 and /WR signals for one extra cycle, but our hardware " generates a shortened /WR signal for our DAC's and muxes. "**************************************************************************** "**************************************************************************** " NOTE: The following property statements are for global properties: "**************************************************************************** PLSI PROPERTY 'PART ispLSI2064E-200LT'; "specifies target Lattice part number PLSI PROPERTY 'ISP ON'; "specifies In-System Programming via JTAG "PLSI PROPERTY 'PIN_FILE myfile'; specifies pin assignment filename PLSI PROPERTY 'PULLUP OFF'; "pullup resistors only on unused I/O pins PLSI PROPERTY 'STRATEGY DELAY'; "optimizes for the least number of logic levels DECLARATIONS [ADDR5..ADDR0] PIN; "(input) Address bus bits, active hi !MS0 PIN; "(input) Sharc Memory Select 0, active lo ADRCLK PIN; "(input) Sharc Address Clock, active l-h !WRDAC0 PIN ISTYPE 'COM'; "(output) Write clock to Dac bank 0 BANK0WR PIN ISTYPE 'COM'; "(output) Mux bank 0 write clock BANK0CLK PIN; "(input) Mux bank 0 address bits latch clock MUX0SEL0 PIN ISTYPE 'REG'; "(output) Mux bank 0 latched address bus bit #1 MUX0SEL1 PIN ISTYPE 'REG'; "(output) Mux bank 0 latched address bus bit #2 MUX0ADR0 PIN ISTYPE 'REG'; "(output) Mux bank 0 latched address bus bit #3 MUX0ADR1 PIN ISTYPE 'REG'; "(output) Mux bank 0 latched address bus bit #4 MUX0ADR2 PIN ISTYPE 'REG'; "(output) Mux bank 0 latched address bus bit #5 !MUX00EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 0 #0 decoded enable !MUX00EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 0 #0 decoded enable !MUX01EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 0 #1 decoded enable !MUX01EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 0 #1 decoded enable !MUX02EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 0 #2 decoded enable !MUX02EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 0 #2 decoded enable !MUX03EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 0 #3 decoded enable !MUX03EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 0 #3 decoded enable !WRDAC1 PIN ISTYPE 'COM'; "(output) Write clock to Dac bank 1 BANK1WR PIN ISTYPE 'COM'; "(output) Mux bank 1 write clock BANK1CLK PIN; "(input) Mux bank 1 address bits latch clock MUX1SEL0 PIN ISTYPE 'REG'; "(output) Mux bank 1 latched address bus bit #1 MUX1SEL1 PIN ISTYPE 'REG'; "(output) Mux bank 1 latched address bus bit #2 MUX1ADR0 PIN ISTYPE 'REG'; "(output) Mux bank 1 latched address bus bit #3 MUX1ADR1 PIN ISTYPE 'REG'; "(output) Mux bank 1 latched address bus bit #4 MUX1ADR2 PIN ISTYPE 'REG'; "(output) Mux bank 1 latched address bus bit #5 !MUX10EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 1 #0 decoded enable !MUX10EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 1 #0 decoded enable !MUX11EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 1 #1 decoded enable !MUX11EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 1 #1 decoded enable !MUX12EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 1 #2 decoded enable !MUX12EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 1 #2 decoded enable !MUX13EN_ABC PIN ISTYPE 'COM'; "(output) Mux bank 1 #3 decoded enable !MUX13EN_DEF PIN ISTYPE 'COM'; "(output) Mux bank 1 #3 decoded enable "**************************************************************************** " NOTE: The following property statements specify " critical paths for minimum propagation delay times: "**************************************************************************** PLSI PROPERTY 'CRIT WRDAC0'; "critical path for ORT bypass PLSI PROPERTY 'CRIT BANK0WR'; "critical path for ORT bypass PLSI PROPERTY 'CRIT WRDAC1'; "critical path for ORT bypass PLSI PROPERTY 'CRIT BANK1WR'; "critical path for ORT bypass PLSI PROPERTY 'SCP MS0 PATH1'; "critical path start for 4-PT bypass PLSI PROPERTY 'ECP WRDAC0 PATH1'; "critical path end for 4-PT bypass PLSI PROPERTY 'SCP ADRCLK PATH2'; "critical path start for 4-PT bypass PLSI PROPERTY 'ECP BANK0WR PATH2'; "critical path end for 4-PT bypass PLSI PROPERTY 'SCP MS0 PATH3'; "critical path start for 4-PT bypass PLSI PROPERTY 'ECP WRDAC1 PATH3'; "critical path end for 4-PT bypass PLSI PROPERTY 'SCP ADRCLK PATH4'; "critical path start for 4-PT bypass PLSI PROPERTY 'ECP BANK1WR PATH4'; "critical path end for 4-PT bypass "**************************************************************************** " NOTE: The following property statements specify " actual pin number assignments: "**************************************************************************** "PLSI PROPERTY 'LOCK mypin number'; specifies pin numbers PLSI PROPERTY 'LOCK WRDAC1 7'; "(output) bank 1 data clock to (MS) DAC 2 //PLSI PROPERTY 'LOCK ADRCLK 11'; "(input) dedicated clock Y0 (UNUSED) //PLSI PROPERTY 'LOCK SRESET 15'; "(input) dedicated reset input pin PLSI PROPERTY 'LOCK MUX0SEL0 28'; "(output) Mux bank 0 select bit 0 PLSI PROPERTY 'LOCK MUX0SEL1 32'; "(output) Mux bank 0 select bit 1 PLSI PROPERTY 'LOCK MUX00EN_ABC 34'; "(output) Mux bank 0 #0 decoded enable PLSI PROPERTY 'LOCK MUX00EN_DEF 30'; "(output) Mux bank 0 #0 decoded enable PLSI PROPERTY 'LOCK WRDAC0 45'; "(output) bank 0 data clock to (LS) DAC 0 PLSI PROPERTY 'RESERVE_PIN 54'; "(output) (active hi) Sharc ACK (UNUSED) PLSI PROPERTY 'RESERVE_PIN 56'; "(input) (active lo) Sharc Write strobe (UNUSED) PLSI PROPERTY 'LOCK ADRCLK 58'; "(input) to product term logic PLSI PROPERTY 'LOCK BANK0WR 59'; "(output) clock to BANK0CLK input PLSI PROPERTY 'LOCK BANK0CLK 62'; "(input) clock Y1 PLSI PROPERTY 'LOCK BANK1CLK 65'; "(input) clock Y2 PLSI PROPERTY 'LOCK BANK1WR 67'; "(output) clock to BANK1CLK input PLSI PROPERTY 'RESERVE_PIN 72'; "(input) (active lo) Sharc Sync.Write (UNUSED) PLSI PROPERTY 'LOCK MS0 78'; "(input) Sharc Memory Select 0 PLSI PROPERTY 'LOCK MUX1SEL0 80'; "(output) Mux bank 1 select bit 0 PLSI PROPERTY 'LOCK MUX1SEL1 84'; "(output) Mux bank 1 select bit 1 PLSI PROPERTY 'LOCK MUX10EN_ABC 86'; "(output) Mux bank 1 #0 decoded enable PLSI PROPERTY 'LOCK MUX10EN_DEF 82'; "(output) Mux bank 1 #0 decoded enable PLSI PROPERTY 'LOCK ADDR0 97'; "(input) Sharc address bus bit 0 PLSI PROPERTY 'LOCK ADDR1 98'; "(input) Sharc address bus bit 1 PLSI PROPERTY 'LOCK ADDR2 95'; "(input) Sharc address bus bit 2 PLSI PROPERTY 'LOCK ADDR3 96'; "(input) Sharc address bus bit 3 PLSI PROPERTY 'LOCK ADDR4 93'; "(input) Sharc address bus bit 4 PLSI PROPERTY 'LOCK ADDR5 94'; "(input) Sharc address bus bit 5 "**************************************************************************** " Following is the truth table: " address: " 543210 DAC: mux0 active: mux1 active: "---------------------------------------------------------------------------- " powerup x I0A,B,C I0A,B,C " 000000 0 I0A,B,C I3D,E,F " 000001 1 I0A,B,C I0A,B,C " 000010 0 I1A,B,C I0A,B,C " 000011 1 I1A,B,C I1A,B,C " 000100 0 I2A,B,C I1A,B,C " 000101 1 I2A,B,C I2A,B,C " 000110 0 I3A,B,C I2A,B,C " 000111 1 I3A,B,C I3A,B,C " 001000 0 I0D,E,F I3A,B,C " 001001 1 I0D,E,F I0D,E,F " 001010 0 I1D,E,F I0D,E,F " 001011 1 I1D,E,F I1D,E,F " 001100 0 I2D,E,F I1D,E,F " 001101 1 I2D,E,F I2D,E,F " 001110 0 I3D,E,F I2D,E,F " 001111 1 I3D,E,F I3D,E,F "**************************************************************************** EQUATIONS BANK0WR = !ADDR0 & MS0 & ADRCLK; "output to BANK0CLK BANK0WR.OE = 1; "always enable BANK0WR BANK1WR = ADDR0 & MS0 & ADRCLK; "output to BANK1CLK BANK1WR.OE = 1; "always enable BANK1WR WRDAC0 = !ADDR0 & MS0 & ADRCLK; "data strobe to DAC bank 0 WRDAC0.OE = 1; "always enable WRDAC0 WRDAC1 = ADDR0 & MS0 & ADRCLK; "data strobe to DAC bank 1 WRDAC1.OE = 1; "always enable WRDAC1 MUX0SEL0.CLK = BANK0CLK; "use decoded address clock MUX0SEL0 := ADDR1; "latch address bit #1 MUX0SEL1.CLK = BANK0CLK; "use decoded address clock MUX0SEL1 := ADDR2; "latch address bit #2 MUX0ADR0.CLK = BANK0CLK; "use decoded address clock MUX0ADR0 := ADDR3; "latch address bit #3 MUX0ADR1.CLK = BANK0CLK; "use decoded address clock MUX0ADR1 := ADDR4; "latch address bit #4 MUX0ADR2.CLK = BANK0CLK; "use decoded address clock MUX0ADR2 := ADDR5; "latch address bit #5 MUX00EN_ABC = !MUX0ADR2 & !MUX0ADR1 & !MUX0ADR0; "000 MUX00EN_ABC.OE = 1; "output always enabled MUX00EN_DEF = !MUX0ADR2 & !MUX0ADR1 & MUX0ADR0; "001 MUX00EN_DEF.OE = 1; "output always enabled MUX01EN_ABC = !MUX0ADR2 & MUX0ADR1 & !MUX0ADR0; "010 MUX01EN_ABC.OE = 1; "output always enabled MUX01EN_DEF = !MUX0ADR2 & MUX0ADR1 & MUX0ADR0; "011 MUX01EN_DEF.OE = 1; "output always enabled MUX02EN_ABC = MUX0ADR2 & !MUX0ADR1 & !MUX0ADR0; "100 MUX02EN_ABC.OE = 1; "output always enabled MUX02EN_DEF = MUX0ADR2 & !MUX0ADR1 & MUX0ADR0; "101 MUX02EN_DEF.OE = 1; "output always enabled MUX03EN_ABC = MUX0ADR2 & MUX0ADR1 & !MUX0ADR0; "110 MUX03EN_ABC.OE = 1; "output always enabled MUX03EN_DEF = MUX0ADR2 & MUX0ADR1 & MUX0ADR0; "111 MUX03EN_DEF.OE = 1; "output always enabled MUX1SEL0.CLK = BANK1CLK; "use decoded address clock MUX1SEL0 := ADDR1; "latch address bit #1 MUX1SEL1.CLK = BANK1CLK; "use decoded address clock MUX1SEL1 := ADDR2; "latch address bit #2 MUX1ADR0.CLK = BANK1CLK; "use decoded address clock MUX1ADR0 := ADDR3; "latch address bit #3 MUX1ADR1.CLK = BANK1CLK; "use decoded address clock MUX1ADR1 := ADDR4; "latch address bit #4 MUX1ADR2.CLK = BANK1CLK; "use decoded address clock MUX1ADR2 := ADDR5; "latch address bit #5 MUX10EN_ABC = !MUX1ADR2 & !MUX1ADR1 & !MUX1ADR0; "000 MUX10EN_ABC.OE = 1; "output always enabled MUX10EN_DEF = !MUX1ADR2 & !MUX1ADR1 & MUX1ADR0; "001 MUX10EN_DEF.OE = 1; "output always enabled MUX11EN_ABC = !MUX1ADR2 & MUX1ADR1 & !MUX1ADR0; "010 MUX11EN_ABC.OE = 1; "output always enabled MUX11EN_DEF = !MUX1ADR2 & MUX1ADR1 & MUX1ADR0; "011 MUX11EN_DEF.OE = 1; "output always enabled MUX12EN_ABC = MUX1ADR2 & !MUX1ADR1 & !MUX1ADR0; "100 MUX12EN_ABC.OE = 1; "output always enabled MUX12EN_DEF = MUX1ADR2 & !MUX1ADR1 & MUX1ADR0; "101 MUX12EN_DEF.OE = 1; "output always enabled MUX13EN_ABC = MUX1ADR2 & MUX1ADR1 & !MUX1ADR0; "110 MUX13EN_ABC.OE = 1; "output always enabled MUX13EN_DEF = MUX1ADR2 & MUX1ADR1 & MUX1ADR0; "111 MUX13EN_DEF.OE = 1; "output always enabled END "****************************************************************************** " End of file LATTEQNS.ABL... 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